1. Field of the Invention
The invention relates particularly to a video-frequency analog-to-digital converting arrangement (ADC) having a high sampling rate and low power consumption.
2. Discussion of the Related Art
In digitizing analog signals, an ADC is essential. In video and any real-time digital signal processing, high sampling rate is required and, in most cases, low power consumption is important.
So far, among many fast ADC architectures, the highest sampling rate is obtained by well-known flash ADC in which 2.sup.n comparators are needed, n being the bit number. The sampling time of a flash ADC depends on the preparation and comparison time needed by each comparator.
An improvement in reducing the number of comparators is realized by using the well-known half-flash ADC (two-step or subranging ADC), in which the digitizing is finished in two steps, a coarse step performed by 2.sup.n/2 comparators, and a fine step performed by another 2.sup.n/2 comparators. For a half-flash ADC the number of comparators needed is 2.sup.(1+n/2), and the sampling time equals at least twice as much as that of a flash ADC. For further reduction of the number of comparators in a half-flash comparator, the coarse and fine comparators may be merged, as described in the article "A 10-bit 5-Msample/s CMOS two-step flash ADC" by Joey Doernberg, Paul R. Gray, and David A. Hodges, IEEE Journal of Solid-State Circuits, vol. 24, pp. 241-249, April 1989. In order to reduce the sampling time of a half-flash ADC to that of a flash ADC, the coarse and fine comparisons can be pipelined, as described in the article "An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H" by Masayuki Ishikawa and Tsuneo Tsukahara, IEEE Journal of Solid-state Circuits, vol. 24, pp. 1485-1491, December 1989.
Among other choices, an ADC having pipelined coarse and fine comparisons can reduce the comparator number to n, if one-bit stages are cascaded, as described in the article "An algorithmic analog-to-digital converter" by R. H. McCharles, V. A. Saletore, W. C. Black, Jr., and D. A. Hodges, IEEE Int. Solid-State Circuits conf. Digest of Tech. Papers, pp. 96-97, Feb. 1977. However, the sampling time of such an ADC is more than the preparation and comparison time needed by each comparator and, because of accumulated error during multiple algorithmic operations, it is difficult to reach high precision.
Instead of one-bit stages, three-bit stages can be cascaded in order to limit the length of the pipeline and to obtain extra correcting bits, as described in the article "A pipelined 5 MHz 9b ADC" by Sthephen H. Lewis, Paul R. Gray, 1987 IEEE Int. Solid-state circuits conf. Diges of Tech. Papers, pp. 210-211, Feb. 1987. However, this will nullify the advantage of such a pipelined ADC.
CMOS is the preferred technology particularly for low power consumption. An auto-zero phase is inevitable for a CMOS comparator when providing an 8-bit resolution or higher. The preparation time mentioned above for each CMOS comparator is quite long. It can be at least twice as long as its comparison time. Therefore, the sampling time of all CMOS ADCs listed above are dominated by the auto-zero phase. One technique, called cyclic auto-zero, for overcoming this problem has been proposed in the article "A 0.8 watts, 10 bits/20 MHz CMOS flash converter based on an original technic called cyclic auro-zero" by Thierry Masson, Proceedings of ESSCIRC'90, pp 121-124, September 1992. Unfortunately, it can only be used in a flash ADC consuming a lot of power.
In order to have high sampling rate and low power consumption, therefore, one way is to develop a better process having a smaller feature size. However, the expenses for such a process is high and there is always a limit to the feature size.